A Regularly Modularized Multiplexer-based Full Adder for Arithmetic Applications

In this paper, we propose a novel multiplexer-based full adder design, denoted as MUXFA, by using regular modules for arithmetic applications. The MUXFA full adder is composed of three identical modules, in which each module separately operates for XOR-XNOR function, sum function, and carry function. The structure of the multiplexer-based full adder can be easily constructed by merely a single multiplexer module, its follows comes the features including fast design time, regular structure, simple layout, and enhanced layout efficiency. Furthermore, n-bit adder can be realized in regular architecture by using a single multiplexer module. The advantages of the design are with design simplicity, design regularity, and integrated-circuit (IC) layout modularity. These characteristics are useful and important in cell-based design especially for increase in IC layout efficiency. Due to the regularity and modularity, the proposed full adder is utilization of nineteen transistors only. Comparing with the open literatures, the transistor count is reduced 26.3% to 47.3% and power-delay-product (PDP) is reduced 48% to 122%. In 16-bit ripple carry adder (RCA) architecture, the proposed adder in power consumption, time delay, and PDP characteristics all are greatly improved, particularly in PDP is reduced about 27.5% to 69.0%. The experimental results show that the multiplexer-based MUXFA full adder is verified to be effective and practical.